In order to improve productivity and shorten production time, it is important to simplify manufacturing steps. In addition, because semiconductor devices are highly integrated, design rules have been further lowered. In addition, a multi-level metal line structure and the associated stack via process have been widely developed and used in order to implement high-speed semiconductor devices. However, in the stack via process, there is a problem in that severe misalignment of the stack via may occur. Therefore, there are problems of photoresist pattern rework and a low yield.
In addition, a conventional method of forming a multi-level metal line has too many complicated manufacturing steps. Therefore, there are demands to simplify the manufacturing steps of the method in order to reduce production costs and shorten product time.
FIGS. 1A to 1D are schematic cross sectional views for explaining steps of a method of forming a multi-level metal line of a conventional semiconductor device.
Referring to FIG. 1A, in the method of forming a multi-level metal line of a conventional semiconductor device, a metal layer 12 is formed on a semiconductor substrate 10 where a predetermined lower structure is formed. Here, a conductive diffusion barrier metal layer 14 is interposed between the metal layer 12 and the substrate 10. In addition, a conductive anti-reflection coating (ARC) layer 16 is formed on the metal layer 12. Next, a patterning process using a photoresist pattern is performed to form a metal line 12, 14, 16. An interlayer insulating layer 18 is formed using a deposition method or the like to cover the entire surface of the resultant structure including the metal line 12, 14, 16. Next, a step difference between the upper portions of the interlayer insulating layer 18 is removed by using a planarization process such as a chemical mechanical polishing (CMP) process.
Referring to FIG. 1B, a patterning process using a photoresist pattern is performed on the interlayer insulating layer 18 to form a via contact hole 20 for exposing the metal line 12, 14, 16. Here, in a state that the thick interlayer insulating layer 18 covers the metal line 12, 14, 16, a photoresist pattern for the via contact hole 20 must be accurately aligned to the metal line 12, 14, 16. Therefore, in a stack via process, an abnormally-etched portion 22 may occur due to misalignment of the photoresist pattern.
The abnormally-etched portion 22 may increase resistance of via contact and degrade reliability of metal lines due to electro-migration (EM).
Referring to FIG. 1C, a conductive diffusion barrier metal layer 24 is formed on the inner side of the via contact hole 20. Subsequently, a metal layer 26 for a via plug is deposited on the entire surface of the resultant structure. Here, the metal layer 26 is made of tungsten (W).
Referring to FIG. 1D, a planarization process such as a CMP process is performed to polish and remove the metal layer 26 and the anti-diffusion coating layer 24 on the interlayer insulating layer 18. As a result, the upper surface of the interlayer insulating layer 18 is exposed and the tungsten (W) is only remained within the via contact hole 20, so that a via plug 26 is formed.
As described above, the conventional method is complicated and, since tungsten (W) is used as a via filling material, resistance of via contact increases. In addition, reliability of metal lines due to electro-migration (EM) is degraded.